1 MD7120 features hvcmos ? technology for high performance all n-mosfet full-bridge driver designed for 200v bridge supply voltage up to 1.0mhz operation frequency greater than 90% ef?ciency designed for low total harmonic distortion single voltage drive power supply +12v smart logic voltage threshold resistor programmable ocp threshold uvp function built-in accurate and adjustable dead time 32-lead qfn package applications class-d audio ampli?er high frequency pwm motor control high frequency switching power supply ultrasound transducer drivers high voltage waveform generator ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? general description the supertex MD7120 is a high voltage, high speed, full-bridge driver. it is ideal for class-d audio ampli?er applications and other high frequency pwm driver applications, such as motor driving. this high- voltage and high-speed driver can also be used for other applications: as a piezo-electric transducer driver; as a mosfet driver in a switched mode power supply; or as a two channel driver for half-bridge power stages. the new ic topology is designed to drive dual n-mosfets as power switches for both the high side and low side. it consists of controller logic circuits, level translators, and a bootstrap ?oating powered gate driver and over current protection circuits without using current sensing resistors. the thresholds of the ocp for the high and low side are resistor-programmable. the power mosfet top drain can be connected to up to +200v while the bottom n-channel mosfet source is grounded. they are designed to provide 3.0a peak driving current with well-matched output impendence and propagation delay on the high and low sides, as well as from device-to-device. the en pin serves a dual purpose: the logic high level is used to compute the threshold voltage level of inputs; and the logic low level disables the outputs. the ic is in a low inductance and thermally enhanced package. typical application circuit high speed, 200v, full h-bridge mosfet driver level tr anslator c1 s1 g2 l1 c3 g1 v dd s2 inb +1.8 or 5.0v logic en ina gn d op f logic +12v av dd +200 v v re f oc p uv p ot p s1 - 4 d1, d3 gs1 - 4 MD7120 rd t r2 v ss c2 s3 g4 l2 g3 v dd s4 +12v +200 v d2 d5 d6 bs 3 d3 rp 2 r3 m3 m4 gs 3 gs 4 r6 r7 d1 rp 1 bs 1 v dd 1 c4 d1 d3 d4 m2 m1 r1 gs 1 gs 2 r4 r5 rp 3 r8 v dd 2 driver driver driver driver level tr anslator ctv monitor level tr anslator level tr anslator
2 MD7120 ordering information device package option 32-lead qfn, 7x7mm body, 1.00mm height (max.), 0.65 pitch MD7120 MD7120k6-g -g indicates package is rohs compliant (green) absolute maximum ratings parameter value v dd , (bs1-s1), (bs3-s3) supply voltage -0.5v to 15v v pp , high voltage supply 10v to +220v en, in a , in b logic input voltage -0.5v to 7.5v opf, open drain output voltage -0.5v to 15v junction operating temperature range -40c to +125c storage temperature -65c to 150c thermal resistance ( ja )* 29.3 o c/w absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. * 1oz, 4-layer, 4x3 pcb sym parameter min typ max units conditions v dd positive drive supply voltage 9.0 12 13 v --- v pp high supply voltage - 150 200 v --- v en en input voltage range 1.8 - 5.0 v --- v pt input positive threshold - - 70 % percent of v en voltage v nt input negative threshold 30 - - % percent of v en voltage v hy input threshold hysteresis 9.0 - 30 % percent of v en voltage i ddq v dd quiescent current, en=0 - 140 - a --- i dden v dd average current - 6.0 - ma ina = inb = 0 (measured) i dd v dd average current at 500khz - 57 - ma ina = inb = 500khz 50%, g1~4 to s1~4 with four 1000pf load capacitors r in input logic impedance to gnd - 250 - k --- c in logic input capacitance - 5.0 10 pf --- gate driver outputs sym parameter min typ max units conditions r hsc sourcing output resistance - 5.0 - i ds = 1.0a r hsk sinking output resistance - 5.0 - i ds = 1.0a r lsc sourcing output resistance - 5.0 - i ds = 1.0a r lsk sinking output resistance - 5.0 - i ds = 1.0a dc electrical characteristics (over operating conditions, unless otherwise speci?ed. v dd = 12v, v pp = 200v, t a = 25c) pin con?guration 1 32 32-lead qfn (k6) (top view) product marking 32-lead qfn (k6) MD7120k6 l l l l l l l l l yyww aaa ccc l = lot number yy = year sealed ww = week seale d a = assembler id c = country of origin = green packaging
3 MD7120 logic table logic input power mosfet output en ina inb a bridge output b bridge output 1 0 0 l l 1 0 1 l h 1 1 0 h l 1 1 1 h h 0 x x hi-z hi-z under voltage and over current / temperature protection (over operating conditions, unless otherwise speci?ed. v dd = 12v, v pp = 200v, t a = 0 to 70c) sym parameter min typ max units conditions v ol_opf opf ?ag output low voltage - - 1.0 v opf = low, i pull_up = 1.0ma v pull_up open drain pull-up voltage - - 15 v i opf = 1.0ma i opf opf sinking current limit - 1.0 1.5 ma --- v uvt v dd rising threshold 6.8 7.8 8.8 v --- v uvh v dd uv hysteresis - 0.6 - v --- i rp1 , i rp3 high-side current reference - 55 - a --- i rp2 low-side current reference - 55 - a --- v gs1-4 gate sense voltage threshold 4.5 6.0 7.5 v reference to s1-4 t otp over-temperature threshold 95 110 120 o c if over temperature, opf low and m1~4 off t oth over-temperature hysteresis - 7.0 - o c --- ac electrical characteristics (over operating conditions, unless otherwise speci?ed. v dd = 12v, v pp = 200v, t a = 0 to 70c) sym parameter min typ max units conditions f s switch frequency - - 1.0 mhz --- t dr switch on delay + dead time - 35 - ns when t dt = min t df switch off delay time - 40 - ns see timing diagram t r output rise time - 28 - ns with 1.0nf load t f output fall time - 29 - ns with 1.0nf load t dm dead time matching - - 5 ns channel to channel t dtr dead time adjustable range 15 - 50 ns rdt = 1.0k to 200k t dta dead time accuracy - 5.0 10 % 15ns to 50ns thd total harmonic distortion - 0.0007 - % time jitter contribution, f j = 10hz, f s = 500khz, f a = 1.0khz t en enable ready time - - 80 ns see timing diagram t pwr_up power-up time - - 200 s see timing diagram
4 MD7120 logic v pt/nt / v en curve 0 0. 5 1. 0 1. 5 2. 0 1. 0 2 .0 3. 0 4 .0 5. 0 0 0. 6v v nt v pt v pt/nt v en switch timing diagram adjustable delay time diagram ocp threshold vs rp1, 2, 3 dead time vs rdt 50 % t dt 50 % 50 % t dt 50 % t dr 50 % t r 10 % 90 % t df 10 % 90 % t f 90 % 10 % 50% g1 or g3 g2 or g4 g1 or g3 ina or inb 0 6 0 1 20 18 0 2 40 30 0 3 60 42 0 4 80 54 0 6 00 0 15 30 45 60 75 90 10 5 12 0 13 5 15 0 rd t (k ) de ad ti me (n s) 10 21 32 43 54 65 76 87 98 10 9 1 20 0 0. 8 1. 6 2. 4 3. 2 4 4. 8 5. 6 6. 4 7. 2 8 rp 1, 2, 3 (k ) oc p th re sh ol d (v )
5 MD7120 pin description pin # name function 1 gnd logic signal ground. 2 avdd logic avdd voltage supply (+12v). not connected to vdd1 or vdd2 internally. 3 ina input logic control of the half-bridge a output. 4 en chip power enable, en = hi chip enabled, en = lo disabled, en resets the opf ? ag latch. 5 inb input logic control of the half-bridge b output. 6 opf open drain output of over/under voltage, over current or temperature ? ag, active = low. 7 vss return of voltage supply. 8 nc not connected. 9 rdt dead time program resistor. 10 s4 low side mosfet source. 11 g4 low side mosfet gate. 12 gs4 low side mosfet gate voltage sense. 13 vdd2 positive voltage supply (+12v). may not connected to vdd1 internally . 14 nc not connected. 15 s3 high side mosfet source. 16 g3 high side mosfet gate. 17 gs3 high side mosfet gate voltage sense. 18 bs3 high side boost external capacitor. 19 d3 high side mosfet drain. 20 rp1 high side program resistor ocp threshold for mosfet m1. 21 rp3 high side program resistor ocp threshold for mosfet m3. 22 d1 high side mosfet drain. 23 bs1 high side boost external capacitor. 24 gs1 high side mosfet gate voltage sense. 25 g1 high side mosfet gate. 26 s1 high side mosfet source. 27 nc not connected. 28 vdd1 positive voltage supply (+12v). may not connected to vdd2 internally . 29 gs2 low side mosfet gate voltage sense. 30 g2 low side mosfet gate. 31 s2 low side mosfet source. 32 rp2 low side program resistor ocp threshold for mosfet m2 and m4. note: the thermal pad must be connected to vss externally.
6 MD7120 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-MD7120 nr062508 32-lead qfn package outline (k6) 7x7mm body, 1.00mm height (max), 0.65mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.25 6.85 5.00* 6.85 5.00* 0.65 bsc 0.45* 0.00 0 o nom 0.90 0.02 0.30 7.00 5.51* 7.00 5.15* 0.55* - - max 1.00 0.05 0.35 7.15 5.25* 7.15 5.25* 0.65* 0.15 14 o jedec registration mo-220, variation vkkc-1, issue k, june 2006 * this dimension is not speci?ed in the original jedec drawing. the value listed is for reference only. drawings not to scale. supertex doc. #: dspd-32qfnk67x7p065, version a061808 notes: details of pin 1 identi?er are optional, but must be located within the indicated area. the pin 1 identi?er may be either a mold, or an embedded metal or marked feature. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. the inner tip of the lead may be either rounded or square. 1. 2. 3. seating plane to p v iew side v iew bottom v iew a a1 d e d2 e b e2 a3 l l1 vi ew b vi ew b 1 note 3 note 2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) 1 32 32
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